Freescale Semiconductor /MKW20Z4 /XCVR /DMA_CTRL

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Interpret as DMA_CTRL

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (0)DMA_I_EN 0 (0)DMA_Q_EN

DMA_I_EN=0, DMA_Q_EN=0

Description

DMA Control

Fields

DMA_I_EN

DMA I Enable

0 (0): Transceiver I channel DMA disabled.

1 (1): Enable the transceiver DMA engine to store RX_DIG I channel outputs to system memory.

DMA_Q_EN

DMA Q Enable

0 (0): Transceiver Q channel DMA disabled.

1 (1): Enable the transceiver DMA engine to store RX_DIG Q channel outputs to system memory.

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